Most of the cryptographic constructions deployed in practical systems today, in particular digital signatures and key-establishment schemes, are vulnerable to attacks using quantum computers. Post-quantum cryptography (PQC) deals with the design and implementation of cryptographic algorithms that are resistant to these attacks. In this paper, we evaluate the NIST's PQC competition candidates with respect to their suitability for the implementation on special hardware platforms. In particular, we focus on the implementability on constrained platforms (e.g., smart cards, small single-board computers) on one side and on the performance on very fast hardware-accelerated platforms (i.e., field-programmable gate arrays - FPGAs) on the other side. Besides the analysis of the candidates' design features affecting the performance on these devices and security aspects, we present also the practical results from the existing implementation on contemporary hardware.