Hardware-Accelerated Post-Quantum Network Traffic Encryptor

Hardware-Accelerated Post-Quantum Network Traffic Encryptor

Hardware-Accelerated Post-Quantum Network Traffic Encryptor

The high-speed quantum-safe encryptor is capable of transparent encryption of up to 100 Gb/s traffic on standard IP network infrastructures. It utilizes hardware-accelerated network interfaces, which enable secure, low-level implementation of all sensitive components, including key agreement protocols, key derivation, and high-speed block ciphers. Only algorithms that are quantum-safe are employed: NIST post-quantum standard ML-KEM for key encapsulation, AES-256-GCM for authenticated encryption, and SHA-3 for hybrid key derivation. Additionally, the support for Quantum Key Distribution (QKD) via ETSI standard GS QKD 014 is provided. The encryptor, as well as its cryptographic and networking components, are commercially available as products and licenses / IP Cores.

Next‑generation IP traffic encryption up to 100 Gb/s

  • Maximum speed, minimal latency, and full transparency for your network infrastructure.

Future‑ready cryptography

  • A combination of traditional methods (ECDH‑512), NIST post‑quantum standards (ML‑KEM‑768), and quantum technologies (ETSI GS QKD 014) ensures data protection even in the era of quantum computers.

Fully quantum‑safe solution

  • Designed to withstand current and future threats — including side‑channel attacks.
Hardware-Accelerated Post-Quantum Network Traffic Encryptor
Hardware-Accelerated Post-Quantum Network Traffic Encryptor

Extreme performance through massive parallelization

  • Optimized for maximum throughput and minimal overhead in demanding environments.

Verified on leading FPGA platforms

  • Implemented and tested on major FPGA platforms: Xilinx and Intel Agilex. Easy integration into existing infrastructure via QSFP28 modules.

Flexible deployment

  • Key components are also available as IP cores for any FPGA or ASIC hardware.

Interested in working with us?

Don’t hesitate to contact us by email or phone. We’ll arrange a meeting and discuss how we can support you. We are always open to new challenges.

Contact: Jan Hajný
E-mail: hajny@vut.cz
phone.: +420 54114 6961

 

The FPGA implementation was developed at the Faculty of Electrical Engineering and Communication of Brno University of Technology, supervised by the National Cyber and Information Security Agency (NUKIB) and supported by the Ministry of the Interior of the Czech Republic under project NESPOQ (VJ01010008, program IMPAKT).